LSI (Large Scale Integration) digital circuits operate in synchronization with clock signals. In the case of large circuit scale, consumption of a significant amount of electric current occurs at a clock transition, thereby generating power supply noise in the power supply voltage, which is known as an IR drop. Such an IR drop causes the power supply voltage to exhibit a voltage change having a frequency range that is determined by the impedances of a power supply line and a stabilizing capacitor. This change generally has a frequency range of approximately 50 MHz to 150 MHz.
A drop in the power supply voltage causes a deterioration in the transition speed of a signal propagating through a signal line in the LSI circuit, which may cause a failure in data transfer in a critical path or the like that has only a small timing margin for signal propagation. In order to avoid such timing error, an LSI such as a processor may adaptively control the operating frequency in response to a voltage drop. To be more specific, the voltage is measured, and an increase in the delay in the data path caused by the voltage drop is estimated, followed by increasing the clock cycle such as to cancel the increase in the delay.
As is generally known, the frequency-division ratio of a PLL (phase-locked loop) circuit may be changed in order to change a clock cycle. This method measures an effect of a voltage drop on the timing, and changes the frequency-division ratio of the PLL circuit based on the measurements to lower the oscillating frequency of the PLL circuit, thereby achieving adaptive frequency control.
This adaptive frequency control involves changing the oscillating frequency by use of the control system of the PLL circuit, so that it takes a long time to set the oscillating frequency of the PLL circuit to a desired frequency after the change in the frequency-division ratio. For example, a time length equivalent to more than 200 cycles of a reference clock may be needed. Such control is still able to make a change in the clock frequency that properly follows a voltage drop when the voltage drop is a slow change (e.g., a change of several tens of kilo hertz in terms of frequency).
An IR drop that occurs in response to an increase in a processor's utilization rate, for example, is a fast change having a frequency range of approximately 50 MHz to 150 MHz as was previously described. Accordingly, the adaptive frequency control that changes the frequency-division ratio of a PLL circuit is unable to make a clock frequency change that follows a voltage drop, thereby failing to avoid timing error.    [Patent Document 1] Japanese Laid-open Patent Publication No. H11-288325    [Patent Document 2] Japanese Laid-open Patent Publication No. 2002-202829    [Non-Patent Document 1] Dong Jiao, Bongjin Kim, and Chris H. Kim, “Design, Modeling, and Test of a Programmable Adaptive Phase-Shifting PLL for Enhancing Clock Data Compensation,” The Journal of Solid-state Circuits, VOL. 47, NO. 10, October 2012, pp 2505-2012    [Non-Patent Document 2] M. S. Floyd, et al., “Runtime power reduction capability of the IBM POWER7+ chip,” IBM J. RES. & DEV. VOL. 57, NO. 6, PAPER 2, November/December 2013, pp 2:1-2:17